#ifndef F28P65X_CMPSS_H
#define F28P65X_CMPSS_H

#ifdef __cplusplus
extern "C" {
#endif

//---------------------------------------------------------------------------
// CMPSS Individual Register Bit Definitions:

struct COMPCTL_BITS
{                            // bits description
    Uint32 COMPHSOURCE  : 1; // 0 High Comparator Source Select
    Uint32 COMPHINV     : 1; // 1 High Comparator Invert Select
    Uint32 CTRIPHSEL    : 2; // 3:2 High Comparator Trip Select
    Uint32 CTRIPOUTHSEL : 2; // 5:4 High Comparator Trip Output Select
    Uint32 ASYNCHEN     : 1; // 6 High Comparator Asynchronous Path Enable
    Uint32 rsvd1        : 1; // 7 Reserved
    Uint32 COMPLSOURCE  : 1; // 8 Low Comparator Source Select
    Uint32 COMPLINV     : 1; // 9 Low Comparator Invert Select
    Uint32 CTRIPLSEL    : 2; // 11:10 Low Comparator Trip Select
    Uint32 CTRIPOUTLSEL : 2; // 13:12 Low Comparator Trip Output Select
    Uint32 ASYNCLEN     : 1; // 14 Low Comparator Asynchronous Path Enable
    Uint32 COMPDACE     : 1; // 15 Comparator/DAC Enable
};

union COMPCTL_REG
{
    Uint32 all;
    struct COMPCTL_BITS bit;
};

struct COMPHYSCTL_BITS
{                        // bits description
    Uint32 COMPHYS : 4;  // 3:0 Comparator Hysteresis Trim
    Uint32 rsvd1   : 12; // 15:4 Reserved
};

union COMPHYSCTL_REG
{
    Uint32 all;
    struct COMPHYSCTL_BITS bit;
};

struct COMPSTS_BITS
{                          // bits description
    Uint32 COMPHSTS   : 1; // 0 High Comparator Status
    Uint32 COMPHLATCH : 1; // 1 High Comparator Latched Status
    Uint32 rsvd1      : 6; // 7:2 Reserved
    Uint32 COMPLSTS   : 1; // 8 Low Comparator Status
    Uint32 COMPLLATCH : 1; // 9 Low Comparator Latched Status
    Uint32 rsvd2      : 6; // 15:10 Reserved
};

union COMPSTS_REG
{
    Uint32 all;
    struct COMPSTS_BITS bit;
};

struct COMPSTSCLR_BITS
{                          // bits description
    Uint32 rsvd1      : 1; // 0 Reserved
    Uint32 HLATCHCLR  : 1; // 1 High Comparator Latched Status Clear
    Uint32 HSYNCCLREN : 1; // 2 High Comparator EPWMSYNCPER Clear Enable
    Uint32 rsvd2      : 6; // 8:3 Reserved
    Uint32 LLATCHCLR  : 1; // 9 Low Comparator Latched Status Clear
    Uint32 LSYNCCLREN : 1; // 10 Low Comparator EPWMSYNCPER Clear Enable
    Uint32 rsvd3      : 5; // 15:11 Reserved
};

union COMPSTSCLR_REG
{
    Uint32 all;
    struct COMPSTSCLR_BITS bit;
};

struct COMPDACHCTL_BITS
{                           // bits description
    Uint32 DACSOURCE   : 1; // 0 DAC Source Control
    Uint32 RAMPSOURCE  : 4; // 4:1 Ramp Generator Source Control
    Uint32 SELREF      : 1; // 5 DAC Reference Select
    Uint32 RAMPLOADSEL : 1; // 6 Ramp Load Select
    Uint32 SWLOADSEL   : 1; // 7 Software Load Select
    Uint32 BLANKSOURCE : 4; // 11:8 EPWMBLANK Source Select
    Uint32 BLANKEN     : 1; // 12 EPWMBLANK Enable
    Uint32 RAMPDIR     : 1; // 13 Ramp Generator Direction
    Uint32 FREESOFT    : 2; // 15:14 Free/Soft Emulation Bits
};

union COMPDACHCTL_REG
{
    Uint32 all;
    struct COMPDACHCTL_BITS bit;
};

struct COMPDACHCTL2_BITS
{                               // bits description
    Uint32 DEENABLE        : 1; // 0 Diode Emulation mode enable
    Uint32 DEACTIVESEL     : 5; // 5:1 DEACTIVE source select
    Uint32 rsvd1           : 2; // 7:6 Reserved
    Uint32 BLANKSOURCEUSEL : 1; // 8 BLANK source upper group select
    Uint32 rsvd2           : 1; // 9 Reserved
    Uint32 RAMPSOURCEUSEL  : 1; // 10 RAMP source upper group select
    Uint32 rsvd3           : 1; // 11 Reserved
    Uint32 XTRIGCFG        : 2; // 13:12 Ramp Generator Cross Trigger Configuration
    Uint32 rsvd4           : 2; // 15:14 Reserved
};

union COMPDACHCTL2_REG
{
    Uint32 all;
    struct COMPDACHCTL2_BITS bit;
};

struct DACHVALS_BITS
{                       // bits description
    Uint32 DACVAL : 12; // 11:0 DAC Value Control
    Uint32 rsvd1  : 4;  // 15:12 Reserved
};

union DACHVALS_REG
{
    Uint32 all;
    struct DACHVALS_BITS bit;
};

struct DACHVALA_BITS
{                       // bits description
    Uint32 DACVAL : 12; // 11:0 DAC Value Control
    Uint32 rsvd1  : 4;  // 15:12 Reserved
};

union DACHVALA_REG
{
    Uint32 all;
    struct DACHVALA_BITS bit;
};

struct RAMPHCTLA_BITS
{                           // bits description
    Uint32 RAMPCLKDIV : 10; // 9:0 Ramp Clock Divider Active Value
    Uint32 rsvd1      : 22; // 31:10 Reserved
};

union RAMPHCTLA_REG
{
    Uint32 all;
    struct RAMPHCTLA_BITS bit;
};

struct RAMPHCTLS_BITS
{                           // bits description
    Uint32 RAMPCLKDIV : 10; // 9:0 Ramp Clock Divider Shadow Value
    Uint32 rsvd1      : 22; // 31:10 Reserved
};

union RAMPHCTLS_REG
{
    Uint32 all;
    struct RAMPHCTLS_BITS bit;
};

struct DACLVALS_BITS
{                       // bits description
    Uint32 DACVAL : 12; // 11:0 DAC Value Control
    Uint32 rsvd1  : 4;  // 15:12 Reserved
};

union DACLVALS_REG
{
    Uint32 all;
    struct DACLVALS_BITS bit;
};

struct DACLVALA_BITS
{                       // bits description
    Uint32 DACVAL : 12; // 11:0 DAC Value Control
    Uint32 rsvd1  : 4;  // 15:12 Reserved
};

union DACLVALA_REG
{
    Uint32 all;
    struct DACLVALA_BITS bit;
};

struct RAMPHDLYA_BITS
{                      // bits description
    Uint32 DELAY : 13; // 12:0 High Ramp Delay Value Active
    Uint32 rsvd1 : 3;  // 15:13 Reserved
};

union RAMPHDLYA_REG
{
    Uint32 all;
    struct RAMPHDLYA_BITS bit;
};

struct RAMPHDLYS_BITS
{                      // bits description
    Uint32 DELAY : 13; // 12:0 High Ramp Delay Value Shadow
    Uint32 rsvd1 : 3;  // 15:13 Reserved
};

union RAMPHDLYS_REG
{
    Uint32 all;
    struct RAMPHDLYS_BITS bit;
};

struct CTRIPLFILCTL_BITS
{                         // bits description
    Uint32 FILTINSEL : 3; // 2:0 Filter Input Select
    Uint32 SAMPWIN   : 6; // 8:3 Sample Window
    Uint32 THRESH    : 6; // 14:9 Majority Voting Threshold
    Uint32 FILINIT   : 1; // 15 Filter Initialization Bit
};

union CTRIPLFILCTL_REG
{
    Uint32 all;
    struct CTRIPLFILCTL_BITS bit;
};

struct CTRIPHFILCTL_BITS
{                         // bits description
    Uint32 FILTINSEL : 3; // 2:0 Filter Input Select
    Uint32 SAMPWIN   : 6; // 8:3 Sample Window
    Uint32 THRESH    : 6; // 14:9 Majority Voting Threshold
    Uint32 FILINIT   : 1; // 15 Filter Initialization Bit
};

union CTRIPHFILCTL_REG
{
    Uint32 all;
    struct CTRIPHFILCTL_BITS bit;
};

struct COMPLOCK_BITS
{                           // bits description
    Uint32 COMPCTL    : 1;  // 0 COMPCTL Lock
    Uint32 COMPHYSCTL : 1;  // 1 COMPHYSCTL Lock
    Uint32 DACCTL     : 1;  // 2 DACCTL Lock
    Uint32 CTRIP      : 1;  // 3 CTRIP Lock
    Uint32 rsvd1      : 1;  // 4 Reserved
    Uint32 rsvd2      : 11; // 15:5 Reserved
};

union COMPLOCK_REG
{
    Uint32 all;
    struct COMPLOCK_BITS bit;
};

struct DACHVALS2_BITS
{                       // bits description
    Uint32 DACVAL : 12; // 11:0 DAC Value Control
    Uint32 rsvd1  : 4;  // 15:12 Reserved
};

union DACHVALS2_REG
{
    Uint32 all;
    struct DACHVALS2_BITS bit;
};

struct DACLVALS2_BITS
{                       // bits description
    Uint32 DACVAL : 12; // 11:0 DAC Value Control
    Uint32 rsvd1  : 4;  // 15:12 Reserved
};

union DACLVALS2_REG
{
    Uint32 all;
    struct DACLVALS2_BITS bit;
};

struct COMPDACLCTL_BITS
{                           // bits description
    Uint32 DACSOURCE   : 1; // 0 DAC Source Control
    Uint32 RAMPSOURCE  : 4; // 4:1 Ramp Generator Source Control
    Uint32 rsvd1       : 1; // 5 Reserved
    Uint32 RAMPLOADSEL : 1; // 6 Ramp Load Select
    Uint32 rsvd2       : 1; // 7 Reserved
    Uint32 BLANKSOURCE : 4; // 11:8 EPWMBLANK Source Select
    Uint32 BLANKEN     : 1; // 12 EPWMBLANK Enable
    Uint32 RAMPDIR     : 1; // 13 Ramp Generator Direction
    Uint32 rsvd3       : 2; // 15:14 Reserved
};

union COMPDACLCTL_REG
{
    Uint32 all;
    struct COMPDACLCTL_BITS bit;
};

struct COMPDACLCTL2_BITS
{                               // bits description
    Uint32 rsvd1           : 8; // 7:0 Reserved
    Uint32 BLANKSOURCEUSEL : 1; // 8 BLANK source upper group select
    Uint32 rsvd2           : 1; // 9 Reserved
    Uint32 RAMPSOURCEUSEL  : 1; // 10 RAMP source upper group select
    Uint32 rsvd3           : 5; // 15:11 Reserved
};

union COMPDACLCTL2_REG
{
    Uint32 all;
    struct COMPDACLCTL2_BITS bit;
};

struct RAMPLCTLA_BITS
{                           // bits description
    Uint32 RAMPCLKDIV : 10; // 9:0 Ramp Clock Divider Active Value
    Uint32 rsvd1      : 22; // 31:10 Reserved
};

union RAMPLCTLA_REG
{
    Uint32 all;
    struct RAMPLCTLA_BITS bit;
};

struct RAMPLCTLS_BITS
{                           // bits description
    Uint32 RAMPCLKDIV : 10; // 9:0 Ramp Clock Divider Shadow Value
    Uint32 rsvd1      : 22; // 31:10 Reserved
};

union RAMPLCTLS_REG
{
    Uint32 all;
    struct RAMPLCTLS_BITS bit;
};

struct RAMPLDLYA_BITS
{                      // bits description
    Uint32 DELAY : 13; // 12:0 Low Ramp Delay Value Active
    Uint32 rsvd1 : 3;  // 15:13 Reserved
};

union RAMPLDLYA_REG
{
    Uint32 all;
    struct RAMPLDLYA_BITS bit;
};

struct RAMPLDLYS_BITS
{                      // bits description
    Uint32 DELAY : 13; // 12:0 Low Ramp Delay Value Shadow
    Uint32 rsvd1 : 3;  // 15:13 Reserved
};

union RAMPLDLYS_REG
{
    Uint32 all;
    struct RAMPLDLYS_BITS bit;
};

struct CTRIPLFILCLKCTL2_BITS
{                            // bits description
    Uint32 CLKPRESCALEU : 8; // 7:0 Sample Clock Prescale Upper Bits
    Uint32 rsvd1        : 8; // 15:8 Reserved
};

union CTRIPLFILCLKCTL2_REG
{
    Uint32 all;
    struct CTRIPLFILCLKCTL2_BITS bit;
};

struct CTRIPHFILCLKCTL2_BITS
{                            // bits description
    Uint32 CLKPRESCALEU : 8; // 7:0 Sample Clock Prescale Upper Bits
    Uint32 rsvd1        : 8; // 15:8 Reserved
};

union CTRIPHFILCLKCTL2_REG
{
    Uint32 all;
    struct CTRIPHFILCLKCTL2_BITS bit;
};

struct CMPSS_REGS
{
    union COMPCTL_REG COMPCTL;         // CMPSS Comparator Control Register, offset:0x00
    union COMPHYSCTL_REG COMPHYSCTL;   // CMPSS Comparator Hysteresis Control Register, offset:0x04
    union COMPSTS_REG COMPSTS;         // CMPSS Comparator Status Register, offset:0x08
    union COMPSTSCLR_REG COMPSTSCLR;   // CMPSS Comparator Status Clear Register, offset:0x0C
    union COMPDACHCTL_REG COMPDACHCTL; // CMPSS High DAC Control Register, offset:0x10
    union COMPDACHCTL2_REG COMPDACHCTL2; // CMPSS High DAC Control Register 2, offset:0x14
    union DACHVALS_REG DACHVALS;         // CMPSS High DAC Value Shadow Register, offset:0x18
    union DACHVALA_REG DACHVALA;         // CMPSS High DAC Value Active Register, offset:0x1C
    Uint32 RAMPHREFA;                    // CMPSS High Ramp Reference Active Register, offset:0x20
    Uint32 RAMPHREFS;                    // CMPSS High Ramp Reference Shadow Register, offset:0x24
    Uint32 RAMPHSTEPVALA;                // CMPSS High Ramp Step Value Active Register, offset:0x28
    union RAMPHCTLA_REG RAMPHCTLA;       // CMPSS High Ramp Control Active Register, offset:0x2C
    Uint32 RAMPHSTEPVALS;                // CMPSS High Ramp Step Value Shadow Register, offset:0x30
    union RAMPHCTLS_REG RAMPHCTLS;       // CMPSS High Ramp Control Shadow Register, offset:0x34
    Uint32 RAMPHSTS;                     // CMPSS High Ramp Status Register, offset:0x38
    union DACLVALS_REG DACLVALS;         // CMPSS Low DAC Value Shadow Register, offset:0x3C
    union DACLVALA_REG DACLVALA;         // CMPSS Low DAC Value Active Register, offset:0x40
    union RAMPHDLYA_REG RAMPHDLYA;       // CMPSS High Ramp Delay Active Register, offset:0x44
    union RAMPHDLYS_REG RAMPHDLYS;       // CMPSS High Ramp Delay Shadow Register, offset:0x48
    union CTRIPLFILCTL_REG CTRIPLFILCTL; // CTRIPL Filter Control Register, offset:0x4C
    Uint32 CTRIPLFILCLKCTL;              // CTRIPL Filter Clock Control Register, offset:0x50
    union CTRIPHFILCTL_REG CTRIPHFILCTL; // CTRIPH Filter Control Register, offset:0x54
    Uint32 CTRIPHFILCLKCTL;              // CTRIPH Filter Clock Control Register, offset:0x58
    union COMPLOCK_REG COMPLOCK;         // CMPSS Lock Register, offset:0x5C
    union DACHVALS2_REG DACHVALS2;       // CMPSS High DAC Value Shadow Register 2, offset:0x60
    union DACLVALS2_REG DACLVALS2;       // CMPSS Low DAC Value Shadow Register 2, offset:0x64
    union COMPDACLCTL_REG COMPDACLCTL;   // CMPSS Low DAC Control Register, offset:0x68
    union COMPDACLCTL2_REG COMPDACLCTL2; // CMPSS Low DAC Control Register 2, offset:0x6C
    Uint32 RAMPLREFA;                    // CMPSS Low Ramp Reference Active Register, offset:0x70
    Uint32 RAMPLREFS;                    // CMPSS Low Ramp Reference Shadow Register, offset:0x74
    Uint32 RAMPLSTEPVALA;                // CMPSS Low Ramp Step Value Active Register, offset:0x78
    union RAMPLCTLA_REG RAMPLCTLA;       // CMPSS Low Ramp Control Active Register, offset:0x7C
    Uint32 RAMPLSTEPVALS;                // CMPSS Low Ramp Step Value Shadow Register, offset:0x80
    union RAMPLCTLS_REG RAMPLCTLS;       // CMPSS Low Ramp Control Shadow Register, offset:0x84
    Uint32 RAMPLSTS;                     // CMPSS Low Ramp Status Register, offset:0x88
    union RAMPLDLYA_REG RAMPLDLYA;       // CMPSS Low Ramp Delay Active Register, offset:0x8C
    union RAMPLDLYS_REG RAMPLDLYS;       // CMPSS Low Ramp Delay Shadow Register, offset:0x90
    union CTRIPLFILCLKCTL2_REG
        CTRIPLFILCLKCTL2; // CTRIPL Filter Clock Control Register 2, offset:0x94
    union CTRIPHFILCLKCTL2_REG
        CTRIPHFILCLKCTL2; // CTRIPH Filter Clock Control Register 2, offset:0x98
};

//---------------------------------------------------------------------------
// CMPSS External References & Function Declarations:
//
extern volatile struct CMPSS_REGS Cmpss1Regs;
extern volatile struct CMPSS_REGS Cmpss2Regs;
extern volatile struct CMPSS_REGS Cmpss3Regs;
extern volatile struct CMPSS_REGS Cmpss4Regs;
extern volatile struct CMPSS_REGS Cmpss5Regs;
extern volatile struct CMPSS_REGS Cmpss6Regs;
extern volatile struct CMPSS_REGS Cmpss7Regs;
extern volatile struct CMPSS_REGS Cmpss8Regs;
extern volatile struct CMPSS_REGS Cmpss9Regs;
extern volatile struct CMPSS_REGS Cmpss10Regs;
extern volatile struct CMPSS_REGS Cmpss11Regs;

#ifdef __cplusplus
}
#endif /* extern "C" */

#endif

//===========================================================================
// End of file.
//===========================================================================
